1. Field
Example embodiments relate to a semiconductor memory device, for example, to a non-volatile semiconductor memory device which may recover data when an error is generated in the data of the non-volatile semiconductor memory device, and a data recovery method.
2. Description of the Related Art
A semiconductor memory device may include a volatile semiconductor memory device and/or a non-volatile semiconductor memory device. A volatile semiconductor memory device may include a dynamic random access memory and/or a static random access memory. A volatile semiconductor memory device is may have a high reading and writing speed, but loses stored contents when external power supply is discontinued. A non-volatile semiconductor memory device may include a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and/or an electrically erasable programmable read-only memory (EEPROM). A non-volatile semiconductor memory device maintains stored content, even when external power supply is discontinued. Thus, a non-volatile semiconductor memory device may be used to retain contents that must be kept, regardless of whether power is supplied or not.
With MROM, PROM, and EPROM, it may not be easy for general users to update the content of the memory, because erasing and writing is not easily done by a system itself. However, EEPROM is able to electrically erase and write so as to be increasingly applied to system programming or auxiliary memory devices which require continuous update. For example, a flash EEPROM (hereinafter, referred to as a flash memory device) may be advantageous in the application to a high capacity auxiliary memory device, because of its high integration compared to a conventional EEPROM. Of the flash memory devices, a NAND type flash memory may exhibit higher integration, compared to other NOR or AND type flash memory devices.
A flash memory device may store data in a first logic level and a second logic level according to whether electrons are implanted in a floating gate using an F-N (Fowler-Nordheim) tunneling mechanism. However, the retention characteristic of a flash memory device may deteriorate as time passes. That is, the electrons implanted in the floating gate may leak from the floating gate or free electrons may be inserted in the floating gate as time passes. The leakage or insertion of the electrons may cause generation of data errors.
In the case of the electron leakage, an oxide trap or interface trap may decrease by the cycling of program or erase. In this case, because cell current increases a drop of a threshold voltage between source-drain due to the leakage of electrons, a data error may be generated. Also, in the case of electron insertion, because the cell current decreases due to an increase of the threshold voltage between the source-drain as mobile charge is inserted in the floating gate, a data error may be generated.
FIG. 1 is a block diagram of a conventional non-volatile semiconductor memory device. Referring to FIG. 1, a non-volatile semiconductor memory device 10 may include a reference current generation block 11, a sense amplifier 13, a data controller 15, a flash memory cell array 17, a row decoder 17-1, a column decoder 17-2, a high voltage generator 18, and an interface/controller 19. To read out data stored in the flash memory cell array 17, when an address received external to the non-volatile semiconductor memory device 10 is input to the row decoder 17-1 and the column decoder 17-2 via the interface/controller 19, the row decoder 17-1 selects a word line of the flash memory cell array 17 based on the address and the column decoder 17-2 selects a bit line of the memory cell array 17 based on the address.
Current output from a memory cell selected by the row decoder 17-1 and the column decoder 17-2 and a reference current output from the reference current generation block 11 are compared by the sense amplifier 13 so as to be divided into a first logic level, for example, “0”, and a second logic level, for example, “1”. The data whose logic level is determined is output to the interface/controller 19 via the data controller 15. Also, the high voltage generator 18 generates a high voltage needed to program or erase data with respect to the flash memory cell array 17.
However, as data retention capability deteriorates, the current output from the flash memory cell array 17 may decrease below the reference current or increase above the reference current. In either case, when the data stored in the flash memory cell array 17 is read out, a data error may be generated.